Semiconductor products require packaged semiconductor assemblies with a high density of devices in a relatively small space. For example, the space available for memory devices, processors, displays and other microfeature devices is continually decreasing in cell phones, personal digital assistants, laptop computers and many other products. One technique to increase the density of semiconductor devices within a given footprint is to stack semiconductor devices and assemblies, and many stacked semiconductor assemblies require adequate electrical interconnects within and between the packages.
Conventional interconnects electrically connect the integrated circuitry of a semiconductor device (such as a die) with other devices or stacked packages. These interconnects can be formed by creating a via in the packaging material and then filling or plugging the via with conductive material. FIG. 1 illustrates an earlier interconnect 100 including a plugged via 110. The via 110 is formed by drilling or etching a hole through an interposer substrate 112. The interconnect is then formed by plating a conductive material 114 into the via 110, and patterning the conductive material 114 so that it is electrically isolated. The remaining void in the via 110 is filled with a conductive material 116 that plugs the via 110. The conductive material 114 electrically connects a pad 117 at a first side of the package with a solder ball 118 (or other conductive feature) at a second side of the package.
One challenge associated with the interconnect 100 in FIG. 1 is the difficulty of achieving uniform metallization in the vias. Non-uniform plating within the vias decreases the quality and integrity of the interconnect. For example, vias having a high aspect ratio (i.e., ratio of the depth to the size of the opening) are especially difficult to consistently plate and fill. Moreover, in certain circumstances the filling process can trap air in the via that can cause the interconnect or assembly to crack as the fill material and the assembly harden. Such non-uniformities in the vias provide inconsistent electrical connections and compromise the integrity of the metallization of the interconnects.
Other challenges associated with existing interconnects are the cost, time and complexity of forming, plating and filling the vias. Forming the vias by an ablation or drilling process typically requires forming individual vias in a sequential manner: this increases the processing time to form the vias. Simultaneously forming the vias by an etching process can be much faster, but etching can result in inconsistent sizes of the vias. It can also be difficult to achieve a dense distribution of the vias with an etching process. Moreover, the plating and filling processing steps following the via formation require additional processing time.